Toward Reliable and Efficient 6G Wireless Communication: A GQSM-QOSTBC-Based Spatial Modulation Framework

Sagarkumar Patel, Dharmendra Chauhan, Hiren Mewada, Harishkumar B Chaudhari, Sagar Kavaiya, Hardik Modi, Imed Ben Dhaou

This paper presents a new spatial modulation framework for future wireless communication networks by combining Generalized Quadrature Spatial Modulation (GQSM) with improved Quasi-Orthogonal Space-Time Block Codes (QOSTBC). The proposed detection method employs channel-matched filtering, coordinate interleaving, and single-symbol maximum likelihood (ML) detection. This design efficiently separates the real and imaginary parts of the signal, resulting in lower computational complexity and reduced Bit Error Rate (BER). Analytical modeling and simulations conducted over Nakagami-m fading channels demonstrate that the proposed system achieves near-maximum likelihood (ML) performance, enhanced BER, full diversity gain, increased spectral efficiency, and reduced outage probability, particularly at high signal to noise ratio (SNR) levels. The proposed scheme achieves full diversity when m=1, and the diversity performance varies with different value of m. As the Nakagami -m fading parameter increases (m>1), the system attains a higher diversity order and improved BER performance. A comparison with other GQSM schemes, such as D-QR and D-QR-IC, demonstrates clear performance improvements with a much lower computational complexity of O(4M). The complexity remains independent of the number of antennas, indicating the RF chain configuration and hardware noise have minimal impact on performance. These advantages make the proposed system scalable, reliable, and energy-efficient for applications like vehicular networks, industrial IoT, and UAV communications, thereby supporting the development of 6G and beyond. Furthermore, a high-level hardware analysis demonstrates that the proposed receiver requires only 192 real multiplications and 136 real additions per codeword for 4-QAM, with fixed computational cost for matched filtering and linearly scalable candidate evaluation. The architecture supports full parallelization of scalar ML searches and achieves near-floating-point accuracy using 8-bit fixed-point arithmetic, enabling efficient DSP and FPGA implementations for real-time applications.