Phase-Locked Loop-Based Strategy for Accurate Blanking Time Allocation Around Zero-Voltage Crossings in Bridgeless PFCs

A. Pigazo, P. Lamo, F. Azcondo, C. Brañas

The totem-pole bridgeless power factor correction (PFC) is becoming a de facto standard in high-end power supply designs due to the efficiency and power density it achieves. However, bridgeless PFCs distort the line current near the grid voltage zero crossings (ZC) because of gate delays, parasitic capacitances, and abrupt switch changes. Various strategies have been proposed to mitigate this issue, such as introducing blanking times for Si/SiC mosfets before the ZC and/or implementing soft-start procedures for GaN HEMTs after the ZC. These around-ZC operating states are typically triggered by detecting a predefined voltage threshold, which performs adequately under ideal conditions. However, distorted grid voltages and noisy measurements lead to imprecise and inconsistent triggering and duration of these around-ZC states. This work proposes leveraging the phase-locked loop (PLL), already used for grid synchronization, by utilizing its grid frequency and phase estimations to minimize the variability of the allocation and duration of the blanking times. Since the proposed strategy relies on grid frequency and phase estimations, it is independent of the employed current control approach and the specific power semiconductor technology. The theoretical analysis evaluates the sensitivity of blanking times to voltage and frequency variations for both the existing and proposed methods. The proposed method is analyzed and validated through simulation and experimentally on a $\text{2.5} \,\mathrm{k}\mathrm{W}$ GaN-based commercial prototype. The proposed strategy reduces the standard deviation of blanking time allocation under harmonic distortion, interharmonics, subharmonics, voltage sags, frequency dynamics, and additive voltage sensing noise, while preserving the overall power quality and efficiency performance of the converter.