arxivcs.PLcs.AR2026-07-21
High-Level Synthesis of Efficient Pipelines with Visibility Control
Jungin Rhee, Minseong Jang, Jaewoo Kim, Jeehoon Kang
High-level synthesis (HLS) raises the abstraction of hardware design from concurrent register-transfer level (RTL) programs to sequential programs. Among the forms of parallelism HLS exploits, pipelining demands fine-grained control over pipeline structure and hazard resolution t…