arxivcs.NI2026-07-19
DAN-Scheduler: Deterministic Three-Stage Co-Optimization of Scheduling, Memory Layout, and Pipeline Overlap for General-Purpose NPUs
Neural Processing Units (NPUs) are increasingly deployed for high-throughput, memory-constrained inference, yet their hierarchical on-chip memories and heterogeneous compute and data-movement engines tightly couple execution order, memory placement, and pipeline overlap. Existing…