arxivcs.ARcs.LG2026-07-23
Benchmarking LLMs for Verilog Design Flows
Angshuman Chakravertty, Rahul Koshti, Buddhi Prakash Sharma, Vinay Chamola
Large language models (LLMs) show promise in code generation, but their capabilities to produce correct, synthesizable hardware description language (HDL) code still remain to be properly benchmarked. Existing evaluations are primarily relying on pass@k metrics and lack proper en…