Design and Block-Level Simulation of a 16-Bit SAR ADC in 180 nm CMOS for GPR Applications

Aarushi Kulkarni, B Balaaditya, Dr. Kiran Bailey

This paper presents the design and block-level simulation of a 16-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) implemented in the 180 nm CMOS Process Design Kit (PDK) of the Semiconductor Laboratory (SCL), India, using Cadence Virtuoso with the Spectre simulation engine. The proposed architecture comprises four sub-blocks: a MOS-switch-based Sample-and-Hold (S&H) circuit, a 16-bit R-2R resistive ladder DAC, a dynamic comparator, and a dual-register TSPC-based SAR control logic. Operating from a 1.8 V supply at 20 MHz, the ADC achieves a 1.25 MSPS conversion rate with a theoretical resolution of 27.4 μV/LSB. All four sub-blocks were individually verified through transistor-level simulation. System integration challenges arising from insufficient op-amp gain and DAC settling time are identified and analysed, with corrective measures proposed as future work.