zenodoJournal article2026-07-29
Design and Block-Level Simulation of a 16-Bit SAR ADC in 180 nm CMOS for GPR Applications
Aarushi Kulkarni, B Balaaditya, Dr. Kiran Bailey
This paper presents the design and block-level simulation of a 16-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) implemented in the 180 nm CMOS Process Design Kit (PDK) of the Semiconductor Laboratory (SCL), India, using Cadence Virtuoso with the Sp…