Weave: Verified Netlist-to-Schematic Conversion via Layered Graph Layout
Converting a SPICE netlist into a human-readable schematic is a longstanding problem in electronic design automation: simulators and machine-learning pipelines readily produce netlists, but designers reason about circuits through diagrams. Recent learning-based approaches translate netlists into schematics probabilistically, yet they provide no guarantee that the generated drawing preserves the original connectivity, and their accuracy degrades sharply as circuits grow. We present Weave, a deterministic converter that turns a SPICE netlist into an LTspice .asc schematic using a layered (Sugiyama-style) graph layout, and that certifies every output by a round-trip connectivity check: the generated schematic is re-parsed into a netlist and compared, net for net, against the input. A result is reported as correct only when the two partitions are identical, giving a binary correctness certificate rather than a similarity score. Weave runs entirely client-side as a single dependency-free file and embeds a pin table for 5093 LTspice symbols. On the identical public Circuits-LTSpice test set used by the state-of-the-art LLM converter Schemato (117 circuits, netlisted with LTspice itself), Weave achieves 100% compilation and 100% round-trip-verified connectivity equivalence, compared with Schemato's reported 76% compilation and a graph-edit-distance similarity of 0.35; notably, 73% of that set exceeds the five-component threshold beyond which Schemato reports losing connectivity accuracy. On a larger and harder corpus, the 3460 netlistable circuits of the official Analog Devices LTspice demo collection, Weave verifies exact connectivity for 88.4% of circuits, with the remaining failures concentrated in a single, well-characterized class of dense multi-pin power modules.