Zhifan Jiang — Papers on Cortexa

semantic_scholarProceedings of the 10th Asia-Pacific Workshop on Networking2026-08-05

Turbolearn: Harnessing Accurate and Line-Rate Deep Learning on Programmable Switches

Zhifan Jiang, Longlong Zhu, Jiashuo Yu, Linying Zheng, Chunming Wu, Xiang Chen

TL;DR: Turbolearn co-designs the switch ASIC and switch OS to split inference into a hardware fast path and a software normal path: the fast path performs lightweight feature extraction and classification at line rate, while only low-confidence flows are offloaded to the normal path for full inference.

Intelligent data plane (IDP) enables line-rate traffic analysis by embedding deep learning (DL) models in network switches. However, existing IDP systems must fit the entire inference pipeline into the switch data plane, forcing simplified models and sacrificing accuracy under ti…

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semantic_scholarProceedings of the 10th Asia-Pacific Workshop on Networking2026-08-05

TurboLearn: Harnessing Accurate and Line-Rate Deep Learning on Programmable Switches

Zhifan Jiang, Longlong Zhu, Jiashuo Yu, Linying Zheng, Chunming Wu, Xiang Chen

TL;DR: TurboLearn achieves high accuracy and line-rate performance by co-designing inference across the switch ASIC and switch OS on the same switch by co-designing inference across the switch ASIC and switch OS on the same switch.

The intelligent data plane (IDP) embeds deep learning (DL) models on switches for line-rate traffic analysis, but hardware constraints often force simplified models, reducing accuracy, while complex models like Transformers remain undeployable. We present TurboLearn, which achiev…

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