Turbolearn: Harnessing Accurate and Line-Rate Deep Learning on Programmable Switches
Zhifan Jiang, Longlong Zhu, Jiashuo Yu, Linying Zheng, Chunming Wu, Xiang Chen
TL;DR: Turbolearn co-designs the switch ASIC and switch OS to split inference into a hardware fast path and a software normal path: the fast path performs lightweight feature extraction and classification at line rate, while only low-confidence flows are offloaded to the normal path for full inference.
Intelligent data plane (IDP) enables line-rate traffic analysis by embedding deep learning (DL) models in network switches. However, existing IDP systems must fit the entire inference pipeline into the switch data plane, forcing simplified models and sacrificing accuracy under tight hardware constraints. We present Turbolearn, a framework for accurate and high-performance DL inference in IDP. Turbolearn co-designs the switch ASIC and switch OS to split inference into a hardware fast path and a software normal path: the fast path performs lightweight feature extraction and classification at line rate, while only low-confidence flows are offloaded to the normal path for full inference. This design preserves switch-speed processing for most traffic while enabling more accurate models than prior ASIC-only approaches. We implement Turbolearn on a 32 × 400 Gbps Intel Tofino2 switch and a cluster of commodity servers. Experiments show that Turbolearn maintains Tbps-level line-rate performance and achieves up to 54.9% relative F1-score improvement over prior IDP baselines.