The densification of Long-Term Evolution (LTE) heterogeneous networks (HetNets) enhances spectral efficiency but exacerbates intercell interference (ICI), especially at cell edges. This study proposes an Enhanced Feedforward Neural Network (eFFNN) for adaptive interference mitigation using 12,847 drive-test samples from Port Harcourt. The model integrates advanced techniques such as batch normalization, dropout, and dynamic loss weighting, and is deployed within a MATLAB/Simulink-based LTE HetNet simulation. Results show significant performance gains, including 68% reduction in packet loss, 36.8% improvement in throughput (85.48 Mbps), and 26–32% latency reduction. The model achieves high predictive accuracy with an R² of 0.9969, demonstrating strong effectiveness.
LEGAL REVIEW Serrano García, Eugenio. “Estados Unidos en Europa: ¿compromiso de verdad o repliegue disfrazado?” Boletín CODESEL, vol. 2, no. 10, August 2026, ISSN-e: 3045-7750. Review The future of the transatlantic relationship has become one of…
LEGAL REVIEW Castro Milla, José Manuel. “Análisis técnico-jurídico de las posibilidades de la Artillería Antiaérea ante la Amenaza de los sUAS.” Boletín CODESEL, vol. 2, no. 10, August 2026, ISSN-e: 3045-7750. Review Fe…
Modern fiber-optic communication lines are the fundamental basis of digital infrastructure, however, their operation is associated with growing requirements for reliability, bandwidth and protection from physical and cyber threats, which makes traditional threshold and statistica…
Rural farmers encounter issues regarding market access, crop advisory services, and safe use of pesticides, which results in lower income and productivity. The authors propose the design and evaluation of a smart digital platform for a rural emarketplace with an integrated AI-pow…
Student mental health difficulties such as stress, anxiety, depression and poor sleep frequently go unnoticed until they have already affected attendance, grades and personal wellbeing, because traditional counselling depends on a student voluntarily seeking help. This paper pres…
This paper presents the design and block-level simulation of a 16-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) implemented in the 180 nm CMOS Process Design Kit (PDK) of the Semiconductor Laboratory (SCL), India, using Cadence Virtuoso with the Sp…