A Modular Ring-Oscillator Array Chip for Accurate Stress Testing of CMOS Aging Mechanisms

J. Diaz-Fortuny, E. Bury, R. Degraeve, B. Kaczer

Ring-oscillator (RO) circuits have historically been used to characterize the performance of CMOS technologies, as they can easily expose both process variability and aging through a straightforward circuit structure. ROs are widely employed to study degradation mechanisms such as bias temperature instability (BTI) and hot carrier degradation (HCD), which progressively deteriorate circuit performance over time. Consequently, accurate characterization of CMOS variability at both the device and circuit levels is essential for precise end-of-life prediction of the integrated circuits (ICs). In this context, this article presents a novel IC design that enables the statistical characterization of both process variability and aging phenomena in ROs. Our chip design contains hundreds of ROs, distributed across six electrically isolated modules or subarrays fabricated in a $1 \times 1$ mm die area. Each module provides high testing versatility, allowing individual access to each RO designed in five different threshold-voltage flavors, as well as ROs designed with thick-oxide IO transistors. Each module consists of a fully functional array, equipped with Force-and-Sense biasing and an on-chip heater structure to enable testing at elevated temperatures up to $325~^{\circ } $ C. This design has been implemented in a commercially available 0.9 V, 28 nm HKMG CMOS technology.